Non-volatile memory reduction based on 1-D memory space mapping of a specific set of QC-LDPC codes
1 Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan 701, Taiwan, R.O.C
2 Department of Electro-Optical Engineering, Kun Shan University, Tainan 710, Taiwan, Republic of China
3 Chung-Shan Institute of Science and Technology
EURASIP Journal on Wireless Communications and Networking 2012, 2012:191 doi:10.1186/1687-1499-2012-191Published: 8 June 2012
Supporting a great diversity of multi-rate H-matrices for multiple communication protocols requires a large amount of non-volatile memory, which may consume a large silicon area or logic elements and constrain the implementation of an overall decoder. Therefore, schemes for memory reduction are necessary to make the parity-check storage more compact. This study proposes a specific set of quasi-cyclic low-density parity-check (LDPC) (QC-LDPC) codes which can transfer a traditional two-dimensional (2-D) parity-check matrix (H-matrix) into a one-dimensional (1-D) memory space. Compared to the existing schemes, the proposed codes and memory reduction scheme do achieve significant reduction rates. Within a fixed memory space, many more H-matrices for diverse communication protocols can be saved via the proposed QC-LDPC codes, which are well constructed from modified Welch-Costas sequences. Furthermore, relatively good error performances, which outperform computer-generated random LDPC codes and Sridhara-Fuja-Tanner codes, are also shown in our simulation results. Consequently, we conclude that the proposed QC-LDPC codes can enlarge the capacity for saving much more low-BER (bit error rate) H-matrices within a fixed memory space.